This application claims the priority of Korean Patent Application No. 2003-9139, filed on Feb. 13, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a local interconnection.
2. Description of the Related Art
As the size and design rule of semiconductor devices gradually become smaller and finer, the degree of integration of semiconductor devices increases, and scaling of a metal oxide semiconductor field effect transistor (MOSFET) as an important component constituting semiconductor devices is gradually reduced. However, reduction in scaling of MOSFET causes the length of the effective channel of the transistor gate to be reduced, thereby resulting in punch-through between the source and drain and resulting in a phenomenon referred to as the “short channel” effect. To improve punch-through and short channel effect, elevated source/drain techniques have been introduced. In addition, a type of interconnection referred to as a local interconnection is used in order to enhance the efficiency of the resulting circuit layout.
Methods for forming elevated source/drain and local interconnections are disclosed, for example, in U.S. Pat. No. 5,893,741 and Japanese Patent Publication No. 2000-114262.
U.S. Pat. No. 5,893,741 discloses a method in which single crystal silicon is formed on the exposed source/drain, and poly crystal silicon is formed on an oxidized layer or poly crystal gate by a load-lock LPVD-Si method. Following this, the poly crystal silicon is etched, except for the local interconnection. Finally, a silicided local interconnection and a silicided source/drain are formed by performing silicidation.
Japanese Patent Publication No. 2000-114262 discloses a method in which an insulating film is formed for covering the gate electrode. An amorphous silicon film is then formed on the entire surface of the insulating layer, and then the amorphous silicon film is annealed to form a selective epitaxial layer. Next, the amorphous silicon film except for a local interconnection formation part is removed, and a silicided local interconnection and silicided source/drain are formed by performing silicidation.
However, in the approach disclosed in U.S. Pat. No. 5,893,741, when the poly crystal silicon except the local interconnection formation part is removed, only the poly crystal silicon has to be selectively removed without damaging the underlying single crystal silicon on the source/drain. Also, in the approach disclosed in Japanese Patent Publication No. 2000-114262, when the amorphous silicon except the local interconnection formation part is removed, the amorphous silicon is to be selectively removed without damaging the single crystal silicon on the source/drain regions. Selectively removal of only the poly crystal silicon or amorphous silicon without damaging the underlying single crystal silicon is a difficult process. Thus, the aforementioned techniques are limited in implementation.